Field of the Invention
The present invention relates to a computer memory system.
Background of the Related Art
In a computer, a memory controller contains the logic that enables reading and writing data to memory devices, such as a dual in-line memory module (DIMM) containing a number of dynamic random access modules (DRAM). The memory controller communicates with one or more memory devices over a number of conductive lines, collectively referred to as a “memory bus” having a bus width equal to the number of conductive lines. The memory controller also communicates with a processor over a “system bus” or “front-side bus.” According to instructions received from the processor, the memory controller can write data received from the processor to the memory devices or read data from the memory devices for provision to the processor.
Currently, memory devices are most often coupled to the memory controller through an interface, such as DDR4. This interface provides connection to a single memory device, but also allows a wide, parallelized datapath and a common shared command, address and control path. These memory devices support standard computing applications which require a cache line access from multiple devices in parallel for error correction and reliability. Computer systems such as servers also need high bandwidth and low latency access to the memory devices along with the potential for a high capacity of memory. However, for any common fixed memory bus width, there is a design tradeoff between memory capacity (the amount of data that can be stored in memory) and bandwidth (the rate of data transfer to and from the memory). In other words, as memory capacity is increased, maintaining signal integrity on the memory bus often requires that the bandwidth be reduced. When increasing the number of memory devices to increase capacity, the capacitive loading on the bus increases and makes fast signaling more difficult. Conversely, maintaining signal integrity on the memory bus as bandwidth is increased generally requires reducing memory capacity or re-driving signals, which increases latency (the time delay to send or receive data). Both of these can significantly reduce system performance.